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PI6C180B
Precision 1-18 Clock Buffer
Product Features
* High-speed, to 140 MHz * Low-noise non-inverting 1-18 buffer * Supports up to four SDRAM DIMMs * Low skew (< 250ps) between any two output clocks * I2C Serial Configuration interface * Multiple VDD, VSS pins for noise reduction * 3.3V power supply voltage * Separate Hi-Z pin for testing * 48-pin SSOP package (V)
Description
The PI6C180B, a high-speed low-noise 1-18 noninverting buffer designed for 140 MHz SDRAM clock buffer applications. At power up all SDRAM output are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the 18 output drivers. The output enable (OE) pin may be pulled low to put all outputs in a Hi-Z state. Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips.
Logic Block Diagram
Product Pin Configuration
NC NC VDD0 SDRAM0 SDRAM1 VSS0 VDD1 SDRAM2 SDRAM3 VSS1 BUF_IN VDD2 SDRAM4 SDRAM5 VSS2 VDD3 SDRAM6 SDRAM7 VSS3 VDD4 SDRAM16 VSS4 VDDIIC SDATA 1 2 3 4 5 6 7 8 48-Pin 9 V 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC VDD9 SDRAM15 SDRAM14 VSS9 VDD8 SDRAM13 SDRAM12 VSS8 OE VDD7 SDRAM11 SDRAM10 VSS7 VDD6 SDRAM9 SDRAM8 VSS6 VDD5 SDRAM17 VSS5 VSSIIC SCLOCK
SDRAM0
SDRAM1
BUF_IN SDRAM2
SDRAM3
SDRAM17
OE
SDATA SCLOCK
I2C I/O
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Product Pin Description
Pin 4,5,8,9 13,14,17,18 31,32,35,36 40,41,44,45 21,28 11 38 24 25 Symbol SDRAM[0- 3] SDRAM[4- 7] SDRAM[8- 11] SDRAM[12- 15] SDRAM[16- 17] BUF_IN OE SDATA SCLOCK Type O O O O O I I I/O I/O Power Ground Power Ground Reserved Qty 4 4 4 4 4 1 1 1 1 10 10 1 1 4 De s cription SDRAM Byte 0 clock output SDRAM Byte 1 clock output SDRAM Byte 2 clock output SDRAM Byte 3 clock output SDRAM clock outputs usable for feedback Input for 1- 18 buffer Hi- Z all outputs when held LOW. Has a >100k internal pull- up resistor Data pin for I2C circuitry. Has a >100k internal pull- up resistor Clock pin I2C circuitry. Has a >100k internal pull- up resistor 3.3V power supply for SDRAM buffers Ground for SDRAM buffers 3.3V power supply for I2C circuitry Ground for I2C circuitry Reserved for future modification. No connects
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PI6C180B Precision 1-18 Clock Buffer
3,7,12,16,20, VDD[0- 9] 29,33,37,42,46 6,10,15,19,22, VSS[0- 9] 27,30,34,39,43 23 26 1,2,47,48 VDDIIC VSSIIC NC
OE Functionality
OE 0 1 SDRAM [0-17] Hi- Z BUF_IN Note 1 2
PI6C180B Serial Configuration Map
Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Pin # 18 17 14 13 9 8 5 4 D e s cription SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive)
Note: Inactive means outputs are held LOW and are disabled from switching.
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Notes: 1. Used for test purposes only 2. Buffers are non-inverting
PI6C180 I2C Address Assignment
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W 0
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
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PI6C180B Precision 1-18 Clock Buffer
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C180B is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLOCK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLOCK is HIGH indicates a start condition. A LOW to HIGH transition on SDATAwhile SCLOCK is HIGH is a stop condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW= write to addressed device). If the devices own address is detected, PI6C180B generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. Command Code byte, and 2. Byte Count byte. Although the data bits on these two bytes are dont care, they must be sent and acknowledged. Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 45 44 41 40 36 35 32 31 De s cription SDRAM15 (Act ive/Ina ct ive) SDRAM14 (Act ive/Ina ct ive) SDRAM13 (Act ive/Ina ct ive) SDRAM12 (Act ive/Ina ct ive) SDRAM11 (Act ive/Ina ct ive) SDRAM10 (Act ive/Ina ct ive) SDRAM9 (Act ive/Ina ct ive) SDRAM8 (Act ive/Ina ct ive)
Byte2: Optional Register for Possible Future Requirements (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 21 De s cription SDRAM17 (Act ive/Ina ct ive) SDRAM16 (Act ive/Ina ct ive) (Reser ved) (Reser ved) (Reser ved) (Reser ved) (Reser ved) (Reser ved)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................. -65C to +150C Ambient Temperature with Power Applied .............................. -0C to +70C 3.3V Supply Voltage to Ground Potential .............................. -0.5V to +4.6V DC Input Voltage .................................................................... -0.5V to +4.6V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol IDD IDD IDD Parame te r Supply Current Supply Current Supply Current Te s t Condition BUF_IN = 0 MHz BUF_IN = 66.66 MHz BUF_IN = 100.0 MHz M in. Typ. M ax. 3 230 360 mA Units
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PI6C180B Precision 1-18 Clock Buffer
DC Operating Specifications (VDD = +3.3V 5%, TA = 0C 70C)
Symbol Input Voltage VIH VIL IIL Input high voltage Input low voltage Input leakage current 0 < VIN < VDD VDD 2.0 VSS - 0.3 5 VDD +0.3 0.8 +5 V mA Parame te r Te s t Condition M in. M ax. Units
VDD[0-9] = 3.3V 5% VOH VOL COUT CIN LPIN TA Output high voltage Output low voltage Output pin capacitance Input pin capacitance Pin Inductance Ambient Temperature No Airflow 0 IOH = 1mA IOL = 1mA 2.4 0.4 6 5 7 70 V
pF nH C
SDRAM Clock Buffer Operating Specification
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRHSDRAM tTHSDRAM Parame te r Pull- up current Pull- up current Pull- down current Pull- down current O utput rise edge rate SDRAM only O utput fall edge rate SDRAM only Te s t Conditions M in. Typ. VOUT = 2.0V VOUT = 3.135V VOUT = 1.0V VOUT = 0.4V 3.3V 5% @04V- 2.4V 3.3V 5% @2.4V- 0.4V 1.5 1.5 40 38 4 4 V/ns 40 36 mA M ax. Units
AC Timing
Symbol tSDKP tSDKH tSDKL tSDRISE tSDFALL tPLH tPHL tPZL,tPZH tPLZ,tPHZ Duty Cycle tSDSKW Parame te r SDRAM CLK period SDRAM CLK high time SDRAM CLK low time SDRAM CLK rise time SDRAM CLK fall time SDRAM Buffer LH prop delay SDRAM Buffer HL prop delay SDRAM Buffer Enable delay SDRAM Buffer Disable delay Measured at 1.5V SDRAM Output to Output Skew 66 M Hz M in. 15.0 5.6 5.3 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.5 5.5 8.0 8.0 55 250 M ax. 15.5 100 M Hz M in. 10.0 3.3 3.1 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.5 5.5 8.0 8.0 55 250 M ax. 10.5 133 M Hz M in. 7.5 1.0 1.0 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.5 5.5 8.0 8.0 55 250 % ps ns V/ns M ax. 7.8 ns Units
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Output Buffer Test Point Test Load
PI6C180B Precision 1-18 Clock Buffer
tSDKP tSDKH
3.3V Clocking Interface (TTL)
2.4 1.5 0.4
tSDKL tSDRISE tSDFALL
Input Waveform tplh Output Waveform
1.5V
1.5V
tphl
1.5V
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock SDRAM M in. Load M ax. Load 15 20 Units pF Note s SDRAM DIMM Specification
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
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PI6C180B Precision 1-18 Clock Buffer
PCB Layout Suggestion
1 C1 VDD 2 3 4 5 C2 VSS VDD 6 7 8 9 VSS C3 VDD 10 11 12 13 14 C4 VSS VDD 15 16 17 18 C5 VSS VDD 19 20 21 C6 VSS VDD 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS VSS Via to GND Plane Via to VDD Plane Void in Power Plane VSS VDD C7 VSS VDD C8 VDD VSS C9 VSS VDD 22uF C10 C12 VDD Ferrite Bead VCC C11
Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C1-C11 should be placed as close as possible to their respective VDD.
Recommended capacitor values: C1-C11 .............. 0.1F, ceramic C12 ................. 22F
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PI6C180B Precision 1-18 Clock Buffer
21$+&*
100/66 MHz Clock from Chipset SDRAM
18
22
SDRAM DIMM CI Spec.
Figure 2. Design Guidelines
48-Pin SSOP (V Package)
48
.291 .299 7.39 7.59
.395 .420 10.03 10.67
Gauge Plane .010 0.25 1 .02 0.51 .04 1.01
.620 .630 15.75 16.00
.008 0.20 Nom.
.015 0.381 x 45 .025 0.635
.110 2.79 Max
0-8 .025 BSC 0.635 .008 0.20 .0135 0.34
.008 0.20 .016 0.40
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Table of Dimensions
Body 48 pins (300 mil) Min. Ma x. E (Width) 0.291 0.299 D (Le ngth) 0.620 0.630 A (He ight) 0.095 0.110 e (Pin-to-Pin pitch) 0.025 -
Ordering Information
P/N PI6C180BV D e s cription 48- pin SSO P Package
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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